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Addressing GPU On-Chip Shared Memory Bank Conflicts Using Elastic Pipeline., and . International Journal of Parallel Programming, 41 (3): 400-429 (2013)High-speed Binary Signed-Digit RNS adder with posibit and negabit encoding., , , and . VLSI-SoC, page 58-59. IEEE, (2013)On implementability of Polymorphic Register Files., , and . ReCoSoC, page 1-6. IEEE, (2012)4-D parity codes for soft error correction in aerospace applications., , and . IDT, page 104-109. IEEE, (2011)A Communication Aware Online Task Scheduling Algorithm for FPGA-Based Partially Reconfigurable Systems., , , and . FCCM, page 65-68. IEEE Computer Society, (2010)High-bandwidth Address Generation Unit., , , , and . Signal Processing Systems, 57 (1): 33-44 (2009)March LA: a test for linked memory faults., , , and . ED&TC, page 627. IEEE Computer Society, (1997)Towards domain-specific Instruction-Set Generation., , and . FPL, page 1-4. IEEE, (2014)Manifestation of Precharge Faults in High Speed DRAM Devices., , and . DDECS, page 179-184. IEEE Computer Society, (2007)The State-of-Art and Future Trends in Testing Embedded Memories., , and . MTDT, page 54-59. IEEE Computer Society, (2004)