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Disambiguation of "Nakamura, Yoshiyuki"

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Context-Aware Weblog to Enhance Communication among Participants in a Conference.

, , , , , , , , , , , , , and . WEBIST (1), page 400-407. INSTICC Press, (2006)

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Other publications of authors with the same name

A method of diagnosing single stuck-at faults in combinational circuits., and . Systems and Computers in Japan, 23 (14): 35-44 (1992)A Location-Based Information Support Infrastructure System using CoBIT., , , , , and . PSC, page 63-70. CSREA Press, (2005)Shared At-Speed BIST for Parallel Test of SRAMs with Different Address Sizes., , and . ATS, page 267. IEEE Computer Society, (2008)A Weblog Grounded to the Real World., , , , , , , , , and 5 other author(s). AAAI Spring Symposium: Computational Approaches to Analyzing Weblogs, page 168-175. AAAI, (2006)Integrated and Automated Design-for-Testability Implementation for Cell-Based ICs., , , , and . Asian Test Symposium, page 122-125. IEEE Computer Society, (1997)Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester., , , and . IEEE Trans. VLSI Syst., 15 (7): 790-800 (2007)Context-Aware Weblog to Enhance Communication among Participants in a Conference., , , , , , , , , and 4 other author(s). WEBIST (1), page 400-407. INSTICC Press, (2006)Effect of BIST Pretest on IC Defect Level., , and . IEICE Transactions, 89-D (10): 2626-2636 (2006)Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST., , and . IEICE Transactions, 88-D (6): 1210-1216 (2005)Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch., , , and . IEICE Transactions, 89-D (3): 1165-1172 (2006)