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Predicting future complementary metal-oxide-semiconductor technology - challenges and approaches., , , , , , , and . IET Computers & Digital Techniques, 10 (6): 315-322 (2016)Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation., , , , , , , and . IEEE Micro, 24 (6): 10-20 (2004)Leveraging CPU Electromagnetic Emanations for Voltage Noise Characterization., , , and . MICRO, page 573-585. IEEE Computer Society, (2018)Reducing pipeline energy demands with local DVS and dynamic retiming., , , , , and . ISLPED, page 319-324. ACM, (2004)Optimal Inductance for On-chip RLC Interconnections., , , and . ICCD, page 264-. IEEE Computer Society, (2003)A 1GHz hardware loop-accelerator with razor-based dynamic adaptation for energy-efficient operation., , , and . CICC, page 1-4. IEEE, (2013)Circuit-aware architectural simulation., , , , , and . DAC, page 305-310. ACM, (2004)Design and Optimization of Inductive-Coupling Links for 3-D-ICs., , and . IEEE Trans. VLSI Syst., 27 (3): 711-723 (2019)RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance., , , , , , , and . J. Solid-State Circuits, 44 (1): 32-48 (2009)Applications of Computation-In-Memory Architectures based on Memristive Devices., , , , , , , , , and 3 other author(s). DATE, page 486-491. IEEE, (2019)