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Disambiguation of "Ruiz-Amaya, Jesús"

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Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm.

, , and . IEEE Trans. on Circuits and Systems, 58-I (12): 2816-2828 (2011)

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Chantal Ruiz University of Stuttgart

Braulio Jesús Garcia Ayala University of Stuttgart

Jesus Antonio Martinez Zarate University of Stuttgart

 

Other publications of authors with the same name

An ultra-low power consumption 1-V, 10-bit succesive approximation ADC., , , and . ICECS, page 634-637. IEEE, (2008)A 12-bit CMOS Current Steering D/A Converter for Embedded Systems., , , , , and . APCCAS, page 1671-1674. IEEE, (2006)An embedded 12-bit 80MS/s A/D/A interface for power-line communications in 0.13µm pure digital CMOS technology., , , , , , and . ISCAS (5), page 4626-4629. IEEE, (2005)Behavioral modeling simulation and high-level synthesis of pipeline A/D converters., , , and . ISCAS (6), page 5609-5612. IEEE, (2005)Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm., , and . IEEE Trans. on Circuits and Systems, 58-I (12): 2816-2828 (2011)Accurate Settling-Time Modeling and Design Procedures for Two-Stage Miller-Compensated Amplifiers for Switched-Capacitor Circuits., , and . IEEE Trans. on Circuits and Systems, 56-I (6): 1077-1087 (2009)MATLAB/SIMULINK-Based High-Level Synthesis of Discrete-Time and Continuous-Time Sigma, Delta Modulators., , , , , , and . DATE, page 150-155. IEEE Computer Society, (2004)A power efficient neural spike recording channel with data bandwidth reduction., , , , and . ISCAS, page 1704-1707. IEEE, (2011)Electrical-level synthesis of pipeline ADCs., , and . APCCAS, page 1628-1631. IEEE, (2008)Behavioral modeling of pipeline ADC building blocks., , and . I. J. Circuit Theory and Applications, 40 (6): 571-594 (2012)