%0 Journal Article %1 journals/tcas/Ruiz-AmayaDV09 %A Ruiz-Amaya, Jesús %A Delgado-Restituto, Manuel %A Rodríguez-Vázquez, Ángel %D 2009 %J IEEE Trans. on Circuits and Systems %K dblp %N 6 %P 1077-1087 %T Accurate Settling-Time Modeling and Design Procedures for Two-Stage Miller-Compensated Amplifiers for Switched-Capacitor Circuits. %U http://dblp.uni-trier.de/db/journals/tcas/tcasI56.html#Ruiz-AmayaDV09 %V 56-I

@article{journals/tcas/Ruiz-AmayaDV09, added-at = {2012-05-08T00:00:00.000+0200}, author = {Ruiz-Amaya, Jesús and Delgado-Restituto, Manuel and Rodríguez-Vázquez, Ángel}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2c4af6e2053249cbb18112b5fa6a4de29/dblp}, ee = {http://dx.doi.org/10.1109/TCSI.2008.2008509}, interhash = {1d085b0c06b56db755b884103766f8aa}, intrahash = {c4af6e2053249cbb18112b5fa6a4de29}, journal = {IEEE Trans. on Circuits and Systems}, keywords = {dblp}, number = 6, pages = {1077-1087}, timestamp = {2016-02-02T02:22:31.000+0100}, title = {Accurate Settling-Time Modeling and Design Procedures for Two-Stage Miller-Compensated Amplifiers for Switched-Capacitor Circuits.}, url = {http://dblp.uni-trier.de/db/journals/tcas/tcasI56.html#Ruiz-AmayaDV09}, volume = {56-I}, year = 2009 }