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CCE: A Combined SRAM and Non Volatile Cache for Endurance of Next Generation Multilevel Non Volatile Memories in Embedded Systems.

, , , and . NANOARCH, page 58-64. ACM, (2018)

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Circuit-level modeling and detection of metallic carbon nanotube defects in carbon nanotube FETs., and . DATE, page 841-846. EDA Consortium, San Jose, CA, USA, (2007)A Metric for Assessing the Error Tolerance of Tile Sets for Punctured DNA Self-Assemblies., , and . VTS, page 275-282. IEEE Computer Society, (2008)Optimal Spare Utilization in Repairable and Reliable Memory Cores., , , , and . MTDT, page 64-71. IEEE Computer Society, (2003)A Diagnosis Method for Interconnects in SRAM Based FPGAs., , , and . Asian Test Symposium, page 278-282. IEEE Computer Society, (1998)Testing programmable interconnect systems: an algorithmic approach., , and . Asian Test Symposium, page 311-316. IEEE Computer Society, (2000)A XOR-Tree Based Technique for Constant Testability of Configurable FPGAs., , , and . Asian Test Symposium, page 248-253. IEEE Computer Society, (1997)Embedded Fault-Tolerant Systems., , , and . IEEE Micro, 18 (5): 8-11 (1998)Evaluation and improvement of fault coverage for verification and validation of protocols., , and . SPDP, page 200-207. IEEE Computer Society, (1990)On the minimal test set for single fault location., , and . EURO-DAC, page 265-270. IEEE Computer Society, (1993)Design and Analysis of Inexact Floating-Point Adders., , , , and . IEEE Trans. Computers, 65 (1): 308-314 (2016)