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3.6 A 60pJ/b 300Mb/s 128×8 Massive MIMO precoder-detector in 28nm FD-SOI.

, , , and . ISSCC, page 60-61. IEEE, (2017)

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A 65 nm single stage 28 fJ/cycle 0.12 to 1.2V level-shifter., and . ISCAS, page 990-993. IEEE, (2014)Algorithm and hardware aspects of pre-coding in massive MIMO systems., , , and . ACSSC, page 1144-1148. IEEE, (2015)High throughput constant envelope pre-coder for massive MIMO systems., , , and . ISCAS, page 1502-1505. IEEE, (2015)A < 1 pJ sub-VT cardiac event detector in 65 nm LL-HVT CMOS., , and . VLSI-SoC, page 253-258. IEEE, (2010)3.6 A 60pJ/b 300Mb/s 128×8 Massive MIMO precoder-detector in 28nm FD-SOI., , , and . ISSCC, page 60-61. IEEE, (2017)A Receiver Architecture for Devices in Wireless Body Area Networks., , , , , , , , , and 3 other author(s). IEEE J. Emerg. Sel. Topics Circuits Syst., 2 (1): 82-95 (2012)Ultra low power transceivers for wireless sensors and body area networks., , , , , , , , , and 3 other author(s). ISMICT, page 1-5. IEEE, (2014)A 65-nm CMOS area optimized de-synchronization flow for sub-VT designs., , , , , and . VLSI-SoC, page 380-385. IEEE, (2013)Benchmarking of Standard-Cell Based Memories in the Sub- VT Domain in 65-nm CMOS Technology., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (2): 173-182 (2011)Ultra-Low-Power Error Correction Circuits: Technology Scaling and Sub-VT Operation., and . IEEE Trans. on Circuits and Systems, 59-II (12): 913-917 (2012)