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Working-zone encoding for reducing the energy in microprocessor address buses.

, , and . IEEE Trans. VLSI Syst., 6 (4): 568-572 (1998)

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Energy and thermal tradeoffs in hardware-based load balancing for clustered multi-core architectures implementing power gating.. SASP, page 89-94. IEEE Computer Society, (2008)A Thermal-Friendly Load-Balancing Technique for Multi-Core Processors.. ISQED, page 549-552. IEEE Computer Society, (2008)Variable-size mosaics: A process-variation aware technique to increase the performance of tile-based, massive multi-core processors.. Computers & Electrical Engineering, 37 (6): 1193-1211 (2011)High-level synthesis techniques for reducing the activity of functional units., and . ISLPD, page 99-104. ACM, (1995)Optimizing CMOS Circuits for Low Power Using Transistor Reordering., and . ED&TC, page 219-223. IEEE Computer Society, (1996)Working-zone encoding for reducing the energy in microprocessor address buses., , and . IEEE Trans. VLSI Syst., 6 (4): 568-572 (1998)Speculating to reduce unnecessary power consumption.. ACM Trans. Embedded Comput. Syst., 2 (4): 509-536 (2003)A Process-Variation Aware Technique for Tile-Based, Massive Multicore Processors.. IEEE Comput. Archit. Lett., 8 (2): 52-55 (2009)Extension of the working-zone-encoding method to reduce the energy on the microprocessor data bus., , and . ICCD, page 414-419. (1998)Register-Transfer Level Transformations for Low-Power Data-Paths., and . Integrated Computer-Aided Engineering, 5 (4): 315-332 (1998)