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Light-Weight Cipher Based on Hybrid CMOS/STT-MRAM: Power/Area Analysis., , , , , , and . ISCAS, page 1-5. IEEE, (2019)The Coupled Atom Transistor: A first realization with shallow donors implanted in a FDSOI silicon nanowire., , , , , , , , , and 2 other author(s). ESSDERC, page 147-150. IEEE, (2013)MRAM: from STT to SOT, for security and memory., , , , , , , , and . DCIS, page 1-6. IEEE, (2018)Mass Production of Silicon MOS-SETs: Can We Live with Nano-Devices' Variability?, , , , , , , , , and 8 other author(s). FET, volume 7 of Procedia Computer Science, page 266-268. Elsevier, (2011)Extremely thin SOI for system-on-chip applications., , , , , , , , , and 10 other author(s). CICC, page 1-4. IEEE, (2012)Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities., , , , , , , , , and 6 other author(s). ESSDERC, page 121-124. IEEE, (2012)Variability in Fully Depleted MOSFETs., , , , , , and . ICICDT, page 1-3. IEEE, (2012)Impact of a Laser Pulse on a STT-MRAM Bitcell: Security and Reliability Issues., , , , , , , , and . IOLTS, page 243-244. IEEE, (2018)