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Time-Shifted CDS Enhancement of Comparator-Based MDAC for Pipelined ADC Applications., , and . ICECS, page 210-213. IEEE, (2007)Design and Analysis of Noise Tolerant Ring Oscillators Using Maneatis Delay Cells., , , , and . ICECS, page 494-497. IEEE, (2007)LSB-first SAR ADC with bit-repeating for reduced energy consumption., , and . ICECS, page 203-206. IEEE, (2014)Analysis of back-end flash in a 1.5b/stage pipelined ADC., , and . ISCAS, page 2247-2250. IEEE, (2013)Class A+ amplifier with controlled positive feedback for discrete-time signal processing circuits., , , and . ISCAS, page 428-431. IEEE, (2012)Correlated jitter sampling for jitter cancellation in pipelined TDC., , , and . ISCAS, page 810-813. IEEE, (2012)The Analysis and Application of Redundant Multistage ADC Resolution Improvements Through PDF Residue Shaping., , and . IEEE Trans. on Circuits and Systems, 59-I (8): 1733-1742 (2012)Continuous-time filter design optimized for reduced die area., , , and . IEEE Trans. on Circuits and Systems, 51-II (3): 105-110 (2004)A 2.5-V 10-b 120-MSample/s CMOS pipelined ADC based on merged-capacitor switching., , , and . IEEE Trans. on Circuits and Systems, 51-II (5): 269-275 (2004)Domino-Logic-Based ADC for Digital Synthesis., , , and . IEEE Trans. on Circuits and Systems, 58-II (11): 744-747 (2011)