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Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications.

A. Artés, J. Ayala, A. Sathanur, J. Huisken, and F. Catthoor. VLSI-SoC, page 136-141. IEEE, (2011)

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Antonio Raiolo University of Stuttgart

Giuliano Antonio Giacoppo University of Stuttgart

Rafael Antonio Lainez Reyes University of Stuttgart

Jesus Antonio Martinez Zarate University of Stuttgart

Other publications of authors with the same name

Power Impact of Loop Buffer Schemes for Biomedical Wireless Sensor Nodes.A. Artés, J. Ayala, and F. Catthoor. Sensors, 12 (11): 15088-15118 (2012)Survey of Low-Energy Techniques for Instruction Memory Organisations in Embedded Systems.A. Artés, J. Ayala, J. Huisken, and F. Catthoor. Signal Processing Systems, 70 (1): 1-19 (2013)Feasibility analysis of channel equalizers using Kharitonov-type results.F. Pérez-Cruz, D. Docampo, A. Artés, and C. Abdallah. ICASSP (3), page 579-582. IEEE Computer Society, (1993)Energy Efficiency Using Loop Buffer based Instruction Memory Organizations.A. Artés, F. Duarte, M. Ashouei, J. Huisken, J. Ayala, D. Atienza, and F. Catthoor. IWIA, page 59-67. IEEE, (2010)Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications.A. Artés, J. Ayala, A. Sathanur, J. Huisken, and F. Catthoor. VLSI-SoC, page 136-141. IEEE, (2011)Design exploration of a NVM based hybrid instruction memory organization for embedded platforms.M. Komalan, J. Pérez, C. Tenllado, J. Montañana, A. Artés, J. Fernández, and F. Catthoor. Design Autom. for Emb. Sys., 17 (3-4): 459-483 (2013)IMOSIM: Exploration tool for Instruction Memory Organisations based on accurate cycle-level energy modelling.A. Artés, J. Ayala, and F. Catthoor. ICECS, page 893-896. IEEE, (2012)A Configurable and Low-Power Mixed Signal SoC for Portable ECG Monitoring Applications.H. Kim, S. Kim, N. Helleputte, A. Artés, M. Konijnenburg, J. Huisken, C. Hoof, and R. Yazicioglu. IEEE Trans. Biomed. Circuits and Systems, 8 (2): 257-267 (2014)Energy impact in the design space exploration of loop buffer schemes in embedded systems.A. Artés, J. Ayala, R. Fasthuber, P. Raghavan, and F. Catthoor. VLSI-SoC, page 216-221. IEEE, (2013)Multi-iteration wavelet zero-tree coding for image compression.M. Losada, G. Tohumoglu, D. Fraile, and A. Artés. Signal Processing, 80 (7): 1281-1287 (2000)

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Disambiguation of "Artés, Antonio"

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Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications.

Please choose a person to relate this publication to

Antonio Raiolo University of Stuttgart

Giuliano Antonio Giacoppo University of Stuttgart

Rafael Antonio Lainez Reyes University of Stuttgart

Jesus Antonio Martinez Zarate University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Artés, Antonio"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications.

Please choose a person to relate this publication to

Antonio Raiolo University of Stuttgart

Giuliano Antonio Giacoppo University of Stuttgart

Rafael Antonio Lainez Reyes University of Stuttgart

Jesus Antonio Martinez Zarate University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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MSOffice XML

Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications.