%0 Conference Paper %1 conf/vlsi/ArtesASHC11 %A Artés, Antonio %A Ayala, José Luis %A Sathanur, Ashoka Visweswara %A Huisken, Jos %A Catthoor, Francky %B VLSI-SoC %D 2011 %I IEEE %K dblp %P 136-141 %T Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications. %U http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2011.html#ArtesASHC11 %@ 978-1-4577-0171-9

@inproceedings{conf/vlsi/ArtesASHC11, added-at = {2018-11-30T00:00:00.000+0100}, author = {Artés, Antonio and Ayala, José Luis and Sathanur, Ashoka Visweswara and Huisken, Jos and Catthoor, Francky}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2bddc9905eb4cf228e82ff5a8af37752b/dblp}, booktitle = {VLSI-SoC}, crossref = {conf/vlsi/2011soc}, ee = {https://doi.org/10.1109/VLSISoC.2011.6081635}, interhash = {87a5219fb65c0bd4a94b6bfa8f6067de}, intrahash = {bddc9905eb4cf228e82ff5a8af37752b}, isbn = {978-1-4577-0171-9}, keywords = {dblp}, pages = {136-141}, publisher = {IEEE}, timestamp = {2019-09-27T19:32:34.000+0200}, title = {Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications.}, url = {http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2011.html#ArtesASHC11}, year = 2011 }