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Disambiguation of "Rao, Rahul M."

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The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4.

, , , , , , , , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 53 (1): 91-101 (2018)

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Rahul Barthwal University of Stuttgart

M. Nudischer

M. Kratzer

M. Liewald

M. Fittingho

 

Other publications of authors with the same name

Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability., , , , , and . Microelectronics Reliability, 49 (6): 642-649 (2009)SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage., , , and . IEEE Trans. VLSI Syst., 19 (1): 24-32 (2011)The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4., , , , , , , , , and 13 other author(s). IEEE J. Solid State Circuits, 53 (1): 91-101 (2018)Dynamically Pulsed MTCMOS With Bus Encoding for Reduction of Total Power and Crosstalk Noise., , , , and . IEEE Trans. VLSI Syst., 18 (1): 166-170 (2010)Parametric Yield Analysis and Optimization in Leakage Dominated Technologies., , , and . IEEE Trans. VLSI Syst., 15 (6): 613-623 (2007)On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits., , , and . ISQED, page 815-820. IEEE Computer Society, (2008)Adaptive MTCMOS for dynamic leakage and frequency control using variable footer strength., , , and . SoCC, page 147-150. IEEE, (2005)Power-aware global signaling strategies., , , , , and . ISCAS (1), page 604-607. IEEE, (2005)A Local Random Variability Detector With Complete Digital On-Chip Measurement Circuitry., , and . J. Solid-State Circuits, 44 (9): 2616-2623 (2009)Approaches to run-time and standby mode leakage reduction in global buses., , , , , and . ISLPED, page 188-193. ACM, (2004)