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A New FPGA/DSP-Based Parallel Architecture for Real-Time Image Processing.

J. Batlle, J. Martí, P. Ridao, and J. Amat. Real-Time Imaging, 8 (5): 345-356 (2002)

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Efficient learning of reactive robot behaviors with a Neural-Q_learning approach.M. Carreras, P. Ridao, J. Batlle, and T. Nicosevici. IROS, page 1020-1025. IEEE, (2002)Recent trends in control architectures for autonomous underwater vehicles.P. Ridao, J. Batlle, J. Amat, and G. Roberts. Int. J. Systems Science, 30 (9): 1033-1056 (1999)A review on strategies for recognizing natural objects in colour images of outdoor scenes.J. Batlle, A. Casals, J. Freixenet, and J. Martí. Image Vision Comput., 18 (6-7): 515-530 (2000)A comparative review of camera calibrating methods with accuracy evaluation.J. Salvi, X. Armangué, and J. Batlle. Pattern Recognition, 35 (7): 1617-1635 (2002)GARBI: a low-cost underwater vehicle.J. Amat, A. Monferrer, J. Batlle, and X. Cufí. Microprocessors and Microsystems - Embedded Hardware Design, 23 (2): 61-67 (1999)A system to reduce the effect of CCDs saturation.J. Isern, and J. Batlle. ICIP (1), page 1001-1004. (1996)On AUV control architecture.P. Ridao, J. Yuh, J. Batlle, and K. Sugihara. IROS, page 855-860. IEEE, (2000)A built-in educational platform for integrating computer engineering technologies.J. Batlle, J. Martí, and L. Pacheco. ITiCSE, page 229. ACM, (1996)Model-based objects recognition in industrial environments for autonomous vehicles control.J. Martí, J. Batlle, and A. Casals. ICRA, page 1632-1637. IEEE, (1997)A Design of Complementary Community Currencies for Education.J. de la Rosa, J. Batlle, E. Batlle, B. Szymanski, and M. Krishnamoorthy. CSEDU (1), page 410-414. INSTICC Press, (2009)

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Disambiguation of "Batlle, Joan"

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A New FPGA/DSP-Based Parallel Architecture for Real-Time Image Processing.

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Disambiguation of "Batlle, Joan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A New FPGA/DSP-Based Parallel Architecture for Real-Time Image Processing.

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A New FPGA/DSP-Based Parallel Architecture for Real-Time Image Processing.