Author of the publication

Timing Analysis and Optimization: From Devices to Systems (Abstract of Embedded Tutorial).

, and . ASP-DAC, page 345. IEEE, (1998)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Modeling Residual Life of an IC Considering Multiple Aging Mechanisms., and . NATW, page 24-27. IEEE, (2016)An Architecture to Enable Lifetime Full Chip Testability in Chip Multiprocessors., , and . PACT, page 219. IEEE Computer Society, (2011)On Reliability Trojan Injection and Detection., , and . J. Low Power Electronics, 8 (5): 674-683 (2012)Guest Editorial: Special Section on "Autonomous Silicon Validation and Testing of Microprocessors and Microprocessor-Based Systems"., , and . IEEE Trans. VLSI Syst., 15 (5): 493-494 (2007)A Scan Cell Design for Scan-Based Debugging of an SoC With Multiple Clock Domains., , , and . IEEE Trans. on Circuits and Systems, 57-II (7): 561-565 (2010)On Symmetric Error Correcting and All Unidirectional Error Detecting Codes., and . IEEE Trans. Computers, 39 (6): 752-761 (1990)Self-Checking Comparator with One Periodic Output., , , and . IEEE Trans. Computers, 45 (3): 379-380 (1996)An Efficient Technique for Leakage Current Estimation in Nanoscaled CMOS Circuits Incorporating Self-Loading Effects., , , and . IEEE Trans. Computers, 59 (7): 922-932 (2010)Efficient Error-Detection and Recovery Mechanisms for Reliability and Resiliency of Multicores., and . VLSI Design, page 12-13. IEEE Computer Society, (2016)Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques., , , , and . IEEE Trans. Information Forensics and Security, 12 (1): 64-77 (2017)