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Regularized Frequency Domain Equalization Algorithm and its VLSI Implementation., , , and . ISCAS, page 3530-3533. IEEE, (2007)A Frame-Start Detector for a 4×4 MIMO-OFDM System., , , , , and . ICASSP (4), page 425-428. IEEE, (2006)A Real-Time 4-Stream MIMO-OFDM Transceiver: System Design, FPGA Implementation, and Characterization., , and . IEEE Journal on Selected Areas in Communications, 26 (6): 877-889 (2008)A 0.25 μm 0.92 mW per Mb/s Viterbi decoder featuring resonant clocking for ultra-low-power 54 Mb/s WLAN communication., , , , , , , and . CICC, page 451-454. IEEE, (2007)Silicon implementation of an MMSE-based soft demapper for MIMO-BICM., , , , , and . ISCAS, IEEE, (2006)FFT Processor for OFDM Channel Estimation., , , , and . ISCAS, page 1417-1420. IEEE, (2007)Simulation and Emulation of MIMO Wireless Baseband Transceivers., , and . EURASIP J. Wireless Comm. and Networking, (2010)Algorithm and VLSI architecture for linear MMSE detection in MIMO-OFDM systems., , , , , and . ISCAS, IEEE, (2006)VLSI Implementation of a High-Speed Iterative Sorted MMSE QR Decomposition., , , , , and . ISCAS, page 1421-1424. IEEE, (2007)System-level characterization of a real-time 4×4 MIMO-OFDM transceiver on FPGA., , and . EUSIPCO, page 1146-1150. IEEE, (2007)