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Disambiguation of "Reda, Sherief"

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Implications of Integrated CPU-GPU Processors on Thermal and Power Management Techniques.

, , , , , and . CoRR, (2018)

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Other publications of authors with the same name

Power Mapping of Integrated Circuits Using AC-Based Thermography., , and . IEEE Trans. VLSI Syst., 21 (8): 1398-1409 (2013)Power Budgeting Techniques for Data Centers., and . IEEE Trans. Computers, 64 (8): 2267-2278 (2015)New and improved BIST diagnosis methods from combinatorial Group testing theory., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (3): 533-543 (2006)Zero-Change Netlist Transformations: A New Technique for Placement Benchmarking., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (12): 2806-2819 (2006)Mitigating dark-silicon problems using superlattice-based thermoelectric coolers., and . DATE, page 1391-1394. EDA Consortium San Jose, CA, USA / ACM DL, (2013)High-sensitivity hardware trojan detection using multimodal characterization., , , and . DATE, page 1271-1276. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Analyzing the impact of process variations on parametric measurements: Novel models and applications., and . DATE, page 375-380. IEEE, (2009)Identifying the optimal energy-efficient operating points of parallel workloads., , , and . ICCAD, page 608-615. IEEE Computer Society, (2011)Workload-Aware Power Gating Design and Run-Time Management for Massively Parallel GPGPUs., , , , and . ISVLSI, page 242-247. IEEE Computer Society, (2016)Generalized Matrix Factorization Techniques for Approximate Logic Synthesis., and . DATE, page 1289-1292. IEEE, (2019)