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Profile-guided transaction coalescing - lowering transactional overheads by merging transactions.

, , , , and . TACO, 10 (4): 50:1-50:18 (2013)

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EVX: Vector execution on low power EDGE cores., , , , , , and . DATE, page 1-4. European Design and Automation Association, (2014)Refueling: Preventing Wire Degradation due to Electromigration., , , , , and . IEEE Micro, 28 (6): 37-46 (2008)Impact of Parameter Variations on Circuits and Microarchitecture., , , , , , and . IEEE Micro, 26 (6): 30-39 (2006)The Velox Transactional Memory Stack., , , , , , , , , and 14 other author(s). IEEE Micro, 30 (5): 76-87 (2010)JSRAM: A Circuit-Level Technique for Trading-Off Robustness and Capacity in Cache Memories., , , , and . ISVLSI, page 149-154. IEEE Computer Society, (2015)A dynamically reconfigurable architecture for emergency and disaster management in ITS., , , , and . ICCVE, page 479-484. IEEE, (2014)unreadTVar: Extending Haskell Software Transactional Memory for Performance., , , , , and . Trends in Functional Programming, volume 8 of Trends in Functional Programming, page 89-104. Intellect, (2007)Implications of non-volatile memory as primary storage for database management systems., , , , and . SAMOS, page 164-171. IEEE, (2016)Transactional Memory: An Overview., , , , , , and . IEEE Micro, 27 (3): 8-29 (2007)Characterization of the Impact of Soft Errors on Iterative Methods., , , , , and . HiPC, page 203-214. IEEE, (2018)