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Fault Modeling and Testability of CMOS Domino Circuits., , and . CDES, page 21-27. CSREA Press, (2005)Automated energy calculation and estimation for delay-insensitive digital circuits., , , and . Microelectronics Journal, 38 (10-11): 1095-1107 (2007)Test method and scheme for low-power validation in modern SOC integrated circuits., , , , and . VTS, page 1-6. IEEE Computer Society, (2016)Special Session: In-System-Test (IST) Architecture for NVIDIA Drive-AGX Platforms., , , , , , , , , and . VTS, page 1-8. IEEE, (2019)A Novel Graph Coloring Based Solution for Low-Power Scan Shift., , , , and . VTS, page 1-6. IEEE, (2019)Advanced test methodology for complex SoCs., , , , , , and . ITC, page 1-10. IEEE, (2016)DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits., , , , and . IEEE Trans. VLSI Syst., 15 (10): 1155-1159 (2007)High-Speed Energy Estimation for Delay-Insensitive Circuits., , and . CDES, page 35-41. CSREA Press, (2005)Implementation of Design For Test for Asynchronous NCL Designs., , , and . CDES, page 78-84. CSREA Press, (2005)A programmable method for low-power scan shift in SoC integrated circuits., , , , , , and . VTS, page 1-6. IEEE Computer Society, (2016)