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Disambiguation of "Kulkarni, Sarvesh H."

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A High-Density Metal-Fuse Technology Featuring a 1.6 V Programmable Low-Voltage Bit Cell With Integrated 1 V Charge Pumps in 22 nm Tri-Gate CMOS.

, , , , , and . J. Solid-State Circuits, 51 (4): 1003-1008 (2016)

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H. Binz

H. Bungartz

H. Binz

H. Binz

Dr. Helge Steenweg University of Stuttgart

Das Projekt Campus-HUB (C-HUB). Eine Konzeptstudie für die Bibliotheken am Campus Stadtmitte Stuttgart. BuB – Forum Bibliothek und Information, 76 (06): 310-314 (2024)
 

Other publications of authors with the same name

Power distribution techniques for dual VDD circuits., and . ASP-DAC, page 838-843. IEEE, (2006)A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications., , , , , , , , , and 6 other author(s). ISSCC, page 324-606. IEEE, (2007)A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 43 (1): 172-179 (2008)A new algorithm for improved VDD assignment in low power dual VDD systems., , and . ISLPED, page 200-205. ACM, (2004)Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 27 (3): 481-494 (2008)A High-Density Metal-Fuse Technology Featuring a 1.6 V Programmable Low-Voltage Bit Cell With Integrated 1 V Charge Pumps in 22 nm Tri-Gate CMOS., , , , , and . J. Solid-State Circuits, 51 (4): 1003-1008 (2016)A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 μ m 2 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS., , , , , and . J. Solid-State Circuits, 45 (4): 863-868 (2010)High performance level conversion for dual VDD design., and . IEEE Trans. VLSI Syst., 12 (9): 926-936 (2004)An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages., , , , , and . ISVLSI, page 149-154. IEEE Computer Society, (2003)A statistical framework for post-silicon tuning through body bias clustering., , and . ICCAD, page 39-46. ACM, (2006)