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Parallel Error Detection for Leading Zero Anticipation.

, , and . J. Comput. Sci. Technol., 21 (6): 901-906 (2006)

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A scan chain optimization method for diagnosis., , , and . ICCD, page 613-620. IEEE Computer Society, (2015)Testing content addressable memories using instructions and march-like algorithms., , , , , and . ICECS, page 774-777. IEEE, (2008)Godson-3B1500: A 32nm 1.35GHz 40W 172.8GFLOPS 8-core processor., , , , , , , , , and 6 other author(s). ISSCC, page 54-55. IEEE, (2013)Design for Testability Features of Godson-3 Multicore Microprocessor., , , and . J. Comput. Sci. Technol., 26 (2): 302-313 (2011)Design of Low-Cost High-Performance Floating-Point Fused Multiply-Add with Reduced Power., , , , and . VLSI Design, page 206-211. IEEE Computer Society, (2010)A Scalable Scan Architecture for Godson-3 Multicore Microprocessor., , , , , , and . Asian Test Symposium, page 219-224. IEEE Computer Society, (2009)Parallel Error Detection for Leading Zero Anticipation., , and . J. Comput. Sci. Technol., 21 (6): 901-906 (2006)Godson-3B: A 1GHz 40W 8-core 128GFLOPS processor in 65nm CMOS., , , , , , , and . ISSCC, page 76-78. IEEE, (2011)A case study of improving at-speed testing coverage of a gigahertz microprocessor., , , , and . ICECS, page 651-654. IEEE, (2009)A novel design of leading zero anticipation circuit with parallel error detection., , and . ISCAS (1), page 676-679. IEEE, (2005)