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Parallel Error Detection for Leading Zero Anticipation.

, , and . J. Comput. Sci. Technol., 21 (6): 901-906 (2006)

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Testing content addressable memories using instructions and march-like algorithms., , , , , and . ICECS, page 774-777. IEEE, (2008)Pre-Silicon Bug Forecast., , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 33 (3): 451-463 (2014)An Interaction of Coherence Protocols and Memory Consistency Models in DSM Systems., , and . Operating Systems Review, 31 (4): 41-54 (1997)Concerning with On-Chip Network Features to Improve Cache Coherence Protocols for CMPs., , , and . Asia-Pacific Computer Systems Architecture Conference, volume 4697 of Lecture Notes in Computer Science, page 304-314. Springer, (2007)A Graph Model for Investigating Memory Consistency.. ICPADS, page 516-523. IEEE Computer Society, (1994)DMA cache: Using on-chip storage to architecturally separate I/O data from CPU data for improving I/O performance., , , and . HPCA, page 1-12. IEEE Computer Society, (2010)Deterministic Replay Using Global Clock., , , , , and . TACO, 10 (1): 1:1-1:28 (2013)LDet: Determinizing Asynchronous Transfer for Postsilicon Debugging., , , , , , and . IEEE Trans. Computers, 62 (9): 1732-1744 (2013)A Comparison of Two Strategies of Dynamic Data Prefetching in Software DSM., and . IPDPS, page 62. IEEE Computer Society, (2001)The Godson Processors: Its Research, Development, and Contributions., , , and . J. Comput. Sci. Technol., 26 (3): 363-372 (2011)