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Disambiguation of "Lee, Hae-Seung"

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A 12 b 5-to-50 MS/s 0.5-to-1 V Voltage Scalable Zero-Crossing Based Pipelined ADC.

, , and . J. Solid-State Circuits, 47 (7): 1603-1614 (2012)

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Moosung Lee University of Stuttgart

Dongwon Lee University of Stuttgart

Junghwa Lee University of Stuttgart

Ph. D. Benjamin Lee University of Stuttgart

Yoonhee Lee University of Stuttgart

 

Other publications of authors with the same name

A Continuous-Time Sturdy-MASH ΔΣ Modulator in 28 nm CMOS., , and . J. Solid-State Circuits, 50 (12): 2880-2890 (2015)A 12b 5-to-50MS/s 0.5-to-1V voltage scalable zero-crossing based pipelined ADC., , and . ESSCIRC, page 355-358. IEEE, (2011)A 2.9-mW 11-b 20-MS/s pipelined ADC with dual-mode-based digital background calibration., , and . ESSCIRC, page 269-272. IEEE, (2012)Session 26 overview: Nyquist-rate converters: Data converters subcommittee., and . ISSCC, page 456-457. IEEE, (2015)Redundancy in SAR ADCs., , and . ACM Great Lakes Symposium on VLSI, page 283-288. ACM, (2011)Learning to Design Circuits., , , and . CoRR, (2018)Digital Background Calibration in Pipelined ADCs Using Commutated Feedback Capacitor Switching., , and . IEEE Trans. on Circuits and Systems, 55-II (9): 877-881 (2008)A 1 GS/s 10b 18.9 mW Time-Interleaved SAR ADC With Background Timing Skew Calibration., , and . J. Solid-State Circuits, 49 (12): 2846-2856 (2014)A 12b 250 MS/s Pipelined ADC With Virtual Ground Reference Buffers., , and . J. Solid-State Circuits, 50 (12): 2912-2921 (2015)A 12 bit 200 MS/s Zero-Crossing-Based Pipelined ADC With Early Sub-ADC Decision and Output Residue Background Calibration., , , , , , , and . J. Solid-State Circuits, 49 (6): 1366-1382 (2014)