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Multifunction Residue Architectures for Cryptography., and . IEEE Trans. on Circuits and Systems, 61-I (4): 1156-1169 (2014)A Radix-4FFT Using Complex RNS Arithmetic., , , and . IEEE Trans. Computers, 34 (6): 573-576 (1985)Memory accesses reordering for interconnect power reduction in sum-of-products computations., , , , and . IEEE Trans. Signal Processing, 50 (11): 2889-2899 (2002)Novel high-radix residue number system multipliers and adders., and . ISCAS (1), page 451-454. IEEE, (1999)Systematic Design of Multi-Modulus/Multi-Function Residue Number System Processors., and . ISCAS, page 79-82. IEEE, (1994)Execution time comparison of lifting-based 2D wavelet transforms implementations on a VLIW DSP., , and . ISCAS, IEEE, (2006)An RNS barrett modular multiplication architecture., and . ISCAS, page 2229-2232. IEEE, (2014)New power-of-2 RNS scaling scheme for cell-based IC design., and . IEEE Trans. VLSI Syst., 11 (2): 280-283 (2003)Modeling and exploiting spatial locality trade-offs in wavelet-based applications under varying resource requirements., , , , , , and . ACM Trans. Embedded Comput. Syst., 9 (3): 17:1-17:26 (2010)Outage probability of single carrier NOMA systems under I/Q imbalance., , , , , , and . WCNC, page 1-6. IEEE, (2018)