PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Jiang, Wenlong"

Author of the publication

copydeleteadd this publication to your clipboard
28.6 A ±50mV linear-input-range VCO-based neural-recording front-end with digital nonlinearity correction.

, , , , and . ISSCC, page 484-485. IEEE, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Chenming Jiang University of Stuttgart

 

Other publications of authors with the same name

A 0.338 cm3, Artifact-Free, 64-Contact Neuromodulation Platform for Simultaneous Stimulation and Sensing., , , , , , and . IEEE Trans. Biomed. Circuits and Systems, 13 (1): 38-55 (2019)Self-Regulated Wireless Power and Simultaneous 5MB/S Reverse Data over One Pair of Coils., , , , and . VLSI Circuits, page 193-194. IEEE, (2018)Design of ADPLL system for WiMAX applications in 40-nm CMOS., , , , , and . ICECS, page 73-76. IEEE, (2012)28.6 A ±50mV linear-input-range VCO-based neural-recording front-end with digital nonlinearity correction., , , , and . ISSCC, page 484-485. IEEE, (2016)A true full-duplex 32-channel 0.135cm3 neural interface., , , , , , and . BioCAS, page 1-4. IEEE, (2017)Time-to-digital converter (TDC) for WiMAX ADPLL in 40-nm CMOS., , , , and . ECCTD, page 365-368. IEEE, (2011)A ±50-mV Linear-Input-Range VCO-Based Neural-Recording Front-End With Digital Nonlinearity Correction., , , , and . J. Solid-State Circuits, 52 (1): 173-184 (2017)Simultaneous Transmission of Up To 94-mW Self-Regulated Wireless Power and Up To 5-Mb/s Reverse Data Over a Single Pair of Coils., , , and . J. Solid-State Circuits, 54 (4): 1003-1016 (2019)