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Disambiguation of "Kawahito, Shoji"

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A 15b power-efficient pipeline A/D converter using non-slewing closed-loop amplifiers.

, , , , and . CICC, page 117-120. IEEE, (2008)

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Other publications of authors with the same name

An offset compensated class-AB sample-and-hold amplifier using two sampling capacitors., and . IEICE Electronic Express, 5 (22): 962-966 (2008)Low-power motion vector estimation using iterative search block-matching methods and a high-speed non-destructive CMOS image sensor., , , and . IEEE Trans. Circuits Syst. Video Techn., 12 (12): 1084-1092 (2002)A Multiplier Chip with Multiple-Valued Bidirectional Current-Mode Logic Circuits., , and . IEEE Computer, 21 (4): 43-56 (1988)A single-ended CMOS chopper amplifier for 1/f noise reduction of n-channel MOS transistors., and . IEICE Electronic Express, 9 (2): 98-103 (2012)Low-Power Design of High-Speed A/D Converters., , , , and . IEICE Transactions, 88-C (4): 468-478 (2005)An 80μVrms-temporal-noise 82dB-dynamic-range CMOS Image Sensor with a 13-to-19b variable-resolution column-parallel folding-integration/cyclic ADC., , , , , , , , , and . ISSCC, page 400-402. IEEE, (2011)6.4 Single-shot 200Mfps 5×3-aperture compressive CMOS imager., , , , , , , and . ISSCC, page 1-3. IEEE, (2015)A CMOS image sensor for 10Mb/s 70m-range LED-based spatial optical communication., , , , , , and . ISSCC, page 402-403. IEEE, (2010)A 1V 10b 125MSample/s A/D Converter Using Cascade Amp-Sharing and Capacitance Coupling Techniues., , and . ISCAS, page 1031-1034. IEEE, (2006)A bit-serial column parallel processing architecture for on-sensor discrete Fourier transform., , and . ISCAS (4), page 738-741. IEEE, (2001)