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Disambiguation of "Higuchi, Tatsuo"

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A Multiplier Chip with Multiple-Valued Bidirectional Current-Mode Logic Circuits.

, , and . IEEE Computer, 21 (4): 43-56 (1988)

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Other publications of authors with the same name

Design of Multiple-Valued Logic Circuits Using Graph-Based Evolutionary Synthesis., , , and . Multiple-Valued Logic and Soft Computing, 11 (5-6): 519-544 (2005)Formal Design of Arithmetic Circuits Based on Arithmetic Description Language., , , and . IEICE Transactions, 89-A (12): 3500-3509 (2006)Efficient learning of NN-MLP based on individual evolutionary algorithm., and . Neurocomputing, 13 (2-4): 201-215 (1996)Design and implementation of an nmos image processor based on quaternary logic., , and . Systems and Computers in Japan, 18 (3): 92-106 (1987)A Multiplier Chip with Multiple-Valued Bidirectional Current-Mode Logic Circuits., , and . IEEE Computer, 21 (4): 43-56 (1988)Design of a Fault-Tolerant System Based on Knowledge-Engineering Approach and Its Application to a Digital Control System., , and . Systems and Computers in Japan, 19 (12): 81-91 (1988)Design of low-power quaternary CMOS logic circuits., , , and . Systems and Computers in Japan, 17 (3): 93-101 (1986)Synthesis of Multiple-Valued Logic Networks Based on Tree-Type Universal Logic Module., and . IEEE Trans. Computers, 26 (12): 1297-1302 (1977)A Systematic Approach for Designing Redundant Arithmetic Adders Based on Counter Tree Diagrams., , and . IEEE Trans. Computers, 57 (12): 1633-1646 (2008)Minimization of nearest neighbor classifiers based on individual evolutionary algorithm., and . Pattern Recognition Letters, 17 (2): 125-131 (1996)