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Limited bandwidth to affect processor design., , and . IEEE Micro, 17 (6): 55-62 (1997)Dark Silicon and the End of Multicore Scaling., , , , and . IEEE Micro, 32 (3): 122-134 (2012)On-Chip Interconnection Networks of the TRIPS Chip., , , , , , and . IEEE Micro, 27 (5): 41-50 (2007)A NUCA Substrate for Flexible CMP Cache Sharing., , , , , and . IEEE Trans. Parallel Distrib. Syst., 18 (8): 1028-1040 (2007)Billion-Transistor Architectures - Guest Editors' Introduction., and . IEEE Computer, 30 (9): 46-49 (1997)Exploiting Microarchitectural Redundancy For Defect Tolerance., , , and . ICCD, page 481-488. IEEE Computer Society, (2003)Static Energy Reduction Techniques for Microprocessor Caches., , , , and . ICCD, page 276-283. IEEE Computer Society, (2001)Memory Systems., , and . The Computer Science and Engineering Handbook, CRC Press, (1997)Implementation and Evaluation of a Dynamically Routed Processor Operand Network., , , , , , and . NOCS, page 7-17. IEEE Computer Society, (2007)Critical path analysis of the TRIPS architecture., , , , and . ISPASS, page 37-47. IEEE Computer Society, (2006)