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Fast, Interactive Worst-Case Execution Time Analysis With Back-Annotation., , , , , and . IEEE Trans. Industrial Informatics, 8 (2): 366-377 (2012)Direct garbage collection: two-fold speedup for managed language embedded systems., and . IJES, 10 (5): 394-405 (2018)Time-Predictable Computer Architecture.. EURASIP J. Emb. Sys., (2009)Models of Communication for Multicore Processors., , and . ISORC Workshops, page 9-16. IEEE Computer Society, (2015)A time-predictable branch predictor., , and . SAC, page 607-616. ACM, (2019)Hardware Locks with Priority Ceiling Emulation for a Java Chip-Multiprocessor., and . ISORC, page 268-271. IEEE Computer Society, (2015)Restrictions of Java for Embedded Real-Time Systems.. ISORC, page 93-100. IEEE Computer Society, (2004)A Hardware Abstraction Layer in Java., , , and . ACM Trans. Embedded Comput. Syst., 10 (4): 42:1-42:40 (2011)Hardlock: A Concurrent Real-Time Multicore Locking Unit., and . ISORC, page 9-16. IEEE Computer Society, (2018)A Single-Path Chip-Multiprocessor System., , and . SEUS, volume 5860 of Lecture Notes in Computer Science, page 47-57. Springer, (2009)