PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Dutt, Nikil D."

Author of the publication

copydeleteadd this publication to your clipboard
Heat-aware transmission strategies.

, , and . ITA, page 154-162. IEEE, (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

D. Marino

D. Roth

D. Inkermann

D. Roth

D. Roth

 

Other publications of authors with the same name

Customizing Software Toolkits for Embedded Systems-On-Chip., , and . DIPES, volume 189 of IFIP Conference Proceedings, page 87-98. Kluwer, (2000)Cyberphysical-system-on-chip (CPSoC): a self-aware MPSoC paradigm with cross-layer virtual sensing and actuation., , , , and . DATE, page 625-628. ACM, (2015)COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC., and . DATE, page 700-705. European Design and Automation Association, Leuven, Belgium, (2006)Data Cache Sizing for Embedded Processor Applications., , and . DATE, page 925-926. IEEE Computer Society, (1998)Protecting caches against multi-bit errors using embedded erasure coding., , , , and . ETS, page 1-6. IEEE, (2015)Retargetable pipeline hazard detection for partially bypassed processors., , , and . IEEE Trans. VLSI Syst., 14 (8): 791-801 (2006)IDAP: a tool for high-level power estimation of custom array structures., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 23 (9): 1361-1369 (2004)Local memory exploration and optimization in embedded systems., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 18 (1): 3-13 (1999)ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement., , , , and . DATE, page 1246-1251. IEEE Computer Society, (2005)Fast Configurable-Cache Tuning With a Unified Second-Level Cache., , and . IEEE Trans. VLSI Syst., 17 (1): 80-91 (2009)