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Disambiguation of "Gossner, Harald"

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System ESD robustness by co-design of on-chip and on-board protection measures.

, , and . Microelectronics Reliability, 50 (9-11): 1359-1366 (2010)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Univ. -Prof. Dr. -Ing. Harald Garrecht University of Stuttgart

Dr. -Ing. Harald Schönberger University of Stuttgart

Harald Jung University of Stuttgart

Harald Knaus University of Stuttgart

Univ. -Prof. Dr. Harald Gießen University of Stuttgart

 

Other publications of authors with the same name

Reliability aspects of gate oxide under ESD pulse stress., , , , , , , , , and 1 other author(s). Microelectronics Reliability, 49 (12): 1407-1416 (2009)A Fully-Integrated Radio-Frequency Power Amplifier in 28nm CMOS Technology Mounted in BGA Package., , , , and . VLSI Design, page 156-161. IEEE Computer Society, (2016)ESD protection for the deep sub micron regime - a challenge for design methodology.. VLSI Design, page 809-. IEEE Computer Society, (2004)System ESD robustness by co-design of on-chip and on-board protection measures., , and . Microelectronics Reliability, 50 (9-11): 1359-1366 (2010)Device Simulation and Backside Laser Interferometry--Powerful Tools for ESD Protection Development., , , , , , , , and . Microelectronics Reliability, 42 (9-11): 1267-1274 (2002)Do ESD fails in systems correlate with IC ESD robustness?, , , and . Microelectronics Reliability, 49 (9-11): 1079-1085 (2009)Effect of pulse risetime on trigger homogeneity in single finger grounded gate nMOSFET electrostatic discharge protection devices., , , , , , and . Microelectronics Reliability, 41 (9-10): 1385-1390 (2001)RF ESD protection strategies: Codesign vs. low-C protection., , , , , , , , and . Microelectronics Reliability, 47 (7): 1008-1015 (2007)Harnessing the base-pushout effect for ESD protection in bipolar and BiCMOS technologies., , , , , , and . Microelectronics Reliability, 43 (7): 1001-1010 (2003)Contact and junction engineering in bulk FinFET technology for improved ESD/latch-up performance with design trade-offs and its implications on hot carrier reliability., , , and . IRPS, page 3. IEEE, (2018)