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Disambiguation of "Kajihara, Nobuki"

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A Gate-Level EHW Chip: Implementing GA Operations and Reconfigurable Hardware on a Single LSI.

, , , , , , , , , , and . ICES, volume 1478 of Lecture Notes in Computer Science, page 1-12. Springer, (1998)

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Other publications of authors with the same name

MAN-YO: Mixed level parallel logic simulation engine., , and . Systems and Computers in Japan, 20 (10): 31-38 (1989)An Evolvable Hardware Chip and Its Application as a Multi-Function Prosthetic Hand Controller., , , , and . AAAI/IAAI, page 182-187. AAAI Press / The MIT Press, (1999)Evolvable Hardware Chips for Industrial Applications., and . Commun. ACM, 42 (4): 60-66 (1999)Parallel neural network simulation machine: Neuman., , , and . Neural Networks, 1 (Supplement-1): 544 (1988)The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing., , , , , , and . IEEE Trans. Computers, 48 (6): 628-639 (1999)Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHW., , , and . FCCM, page 281-282. IEEE Computer Society, (2000)Real-world applications of analog and digital evolvable hardware ., , , , , , , , , and 1 other author(s). IEEE Trans. Evolutionary Computation, 3 (3): 220-235 (1999)Arithmetic Operation Oriented Reconfigurable Chip: RHW., , , and . FPL, volume 2147 of Lecture Notes in Computer Science, page 618-622. Springer, (2001)SOP: a reconfigurable massively parallel system and its control-data-flow based compiling method., , and . FCCM, page 148-156. IEEE, (1996)SOP: An Adaptive Massively Parallel Computer and its Control-Data-Flow Based Compiling Method., , and . Parcella, volume 96 of Mathematical Research, page 128-136. Akademie Verlag, Berlin, (1996)