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State-based Analysis and UML-driven Equivalence Checking for C++ State Machines.

, , , , , and . FM+AM, volume P-179 of LNI, page 49-62. GI, (2010)

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Optimized Temporal Logic Compilation., and . J. UCS, 9 (2): 120-137 (2003)The simulation semantics of systemC., , , , , and . DATE, page 64-70. IEEE Computer Society, (2001)Coverage Driven Verification applied to Embedded Software., , , , , , and . ISVLSI, page 159-164. IEEE Computer Society, (2007)A Synchronous Language for Modeling and Verifying Real Time and Embedded Systems., , , and . MBMV, page 11-20. HNI-Verlagsschriften, (1998)Structured English for Model Checking Specification., , and . MBMV, page 99-108. VDE, (2000)Beschleunigte Robustheitstests für verhaltensbeschreibende Zustandsmaschinen., , , , , , , and . MBMV, page 161-170. Institut für Angewandte Mikroelektronik und Datentechnik, Fakultät für Informatik und Elektrotechnik, Universität Rostock, (2013)Formal Data Analysis of Timed Finite State Systems., and . ECRTS, page 257-. IEEE Computer Society, (2002)A Visual Approach to Validating System Level Designs., , and . ISSS, page 186-191. ACM / IEEE Computer Society, (2002)Efficient and Customizable Integration of Temporal Properties., , , and . FDL, page 385-397. ECSI, (2005)Towards assertion-based verification of heterogeneous system designs., , , , , , and . DATE, page 1171-1176. IEEE, (2010)