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Expressing embedded systems verification aspects at higher abstraction level - SystemVerilog in Object Constraint Language (SVOCL).

, , and . SysCon, page 1-7. IEEE, (2016)

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Throughput/area optimised pipelined architecture for elliptic curve crypto processor., , , and . IET Computers & Digital Techniques, 13 (5): 361-368 (2019)Parallel Greedy Adaptive Search Algorithm for Steiner Tree Problem.. PDPTA, page 1062-1075. CSREA Press, (2006)Evaluation of ASIPs Design with LISATek., , and . SAMOS, volume 5114 of Lecture Notes in Computer Science, page 177-186. Springer, (2008)Generation of SystemVerilog Observers from SysML and MARTE/CCSL., and . ISORC, page 61-68. IEEE Computer Society, (2016)Expressing embedded systems verification aspects at higher abstraction level - SystemVerilog in Object Constraint Language (SVOCL)., , and . SysCon, page 1-7. IEEE, (2016)Automated Model-Based Test Case Generation for Web User Interfaces (WUI) From Interaction Flow Modeling Language (IFML) Models., , , , and . IEEE Access, (2019)Toward the tools selection in model based system engineering for embedded systems - A systematic literature review., , and . Journal of Systems and Software, (2015)UMLPACE for Modeling and Verification of Complex Business Requirements in Event-Driven Process Chain (EPC)., , , , , and . IEEE Access, (2018)Event-Driven Process Chain for Modeling and Verification of Business Requirements-A Systematic Literature Review., , , , and . IEEE Access, (2018)Corrigendum: Throughput/area optimised pipelined architecture for elliptic curve crypto processor.. IET Comput. Digit. Tech., 15 (1): 77 (2021)