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Analog IP design flow for SoC applications., , , and . ISCAS (4), page 676-679. IEEE, (2003)A technique for DC-offset removal and carrier phase error compensation in integrated wireless receivers., , and . ISCAS (1), page 173-176. IEEE, (2003)Power Supply Noise in SoCs: Metrics, Management, and Measurement., , and . IEEE Design & Test of Computers, 24 (3): 236-244 (2007)A Tunable Clock Buffer for Intra-die PVT Compensation in Single-Edge Clock (SEC) Distribution Networks., and . ISQED, page 572-577. IEEE Computer Society, (2008)Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era., , , , and . IEEE Access, (2019)Mixed-mode simulation and analog multilevel simulation., , and . The Kluwer international series in engineering and computer science Kluwer, (1994)Essential Fault-Tolerance Metrics for NoC Infrastructures., , , , and . IOLTS, page 37-42. IEEE Computer Society, (2007)Identification of Viable Paths Using Binary Decision Diagrams., and . ICCD, page 638-641. IEEE Computer Society, (1991)Single Edge Clock (SEC) Distribution for Improved Latency, Skew, and Jitter Performance., and . VLSI Design, page 214-219. IEEE Computer Society, (2008)Design, Synthesis, and Test of Networks on Chips., , , , and . IEEE Design & Test of Computers, 22 (5): 404-413 (2005)