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Systematic Generation of a Variety of Processor Arrays.

, , and . Parcella, volume 81 of Mathematical Research, page 267-276. Akademie Verlag, Berlin, (1994)

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A Parallel Hardware-Software System for Signal Processing Algorithms., , , , , and . PARELEC, page 215-220. IEEE Computer Society, (2004)A cost model for partial dynamic reconfiguration., and . ICSAMOS, page 182-186. IEEE, (2008)Maximum edge matching for reconfigurable computing., and . IPDPS, IEEE, (2006)Scheduling in Co-Partitioned Array Architectures., and . ASAP, page 219-228. IEEE Computer Society, (1997)Synthesis of efficiently reconfigurable datapaths for reconfigurable computing., and . FPT, page 277-280. IEEE, (2008)Efficient Realization of Data Dependencies in Algorithm Partitioning Under Resource Constraints., and . Euro-Par, volume 4128 of Lecture Notes in Computer Science, page 1181-1191. Springer, (2006)Application of Partitioning Methods for the Design of Parallel Programs for a System of Digital Signal Processors., , and . PARELEC, page 139-143. IEEE Computer Society, (2000)Design and Implementation of Reconfigurable Tasks with Minimum Reconfiguration Overhead., and . ARCS Workshops, volume P-81 of LNI, page 132-141. GI, (2006)Fine grain reconfigurable architectures., , , , , , , , , and 5 other author(s). FPL, page 348. IEEE, (2008)Optimized Data-Reuse in Processor Arrays., and . ASAP, page 315-325. IEEE Computer Society, (2004)