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Disambiguation of "Dighe, Saurabh"

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A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS.

, , , , , , , , , , , , , , , , , , , , and . ISSCC, page 66-68. IEEE, (2012)

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Other publications of authors with the same name

IA-32 Processor with a Wide-Voltage-Operating Range in 32-nm CMOS., , , , and . IEEE Micro, 33 (2): 28-36 (2013)The 48-core SCC Processor: the Programmer's View., , , , , , , , , and 1 other author(s). SC, page 1-11. IEEE, (2010)Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor., , , , , , , , , and 2 other author(s). ISSCC, page 174-175. IEEE, (2010)An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS., , , , , , , , , and 4 other author(s). ISSCC, page 98-589. IEEE, (2007)Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor., , , , , , , , , and 2 other author(s). J. Solid-State Circuits, 46 (1): 184-193 (2011)A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS., , , , , , , , , and 20 other author(s). ISSCC, page 108-109. IEEE, (2010)A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS., , , , , , , , , and 11 other author(s). ISSCC, page 66-68. IEEE, (2012)A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling., , , , , , , , , and 6 other author(s). J. Solid-State Circuits, 46 (1): 173-183 (2011)Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging., , , , , , , , , and 9 other author(s). ISSCC, page 292-604. IEEE, (2007)An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS., , , , , , , , , and 5 other author(s). J. Solid-State Circuits, 43 (1): 29-41 (2008)