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Broadband Impedance Matching for Inductive Interconnect in VLSI Packages., and . ICCD, page 683-688. IEEE Computer Society, (2005)A SAT-Based Scheme to Determine Optimal Fix-Free Codes., , and . DCC, page 169-178. IEEE Computer Society, (2010)Dynamically De-Skewable Clock Distribution Methodology., , and . IEEE Trans. VLSI Syst., 16 (9): 1220-1229 (2008)Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction., , , and . IET Computers & Digital Techniques, 2 (3): 214-229 (2008)Crosstalk avoidance codes for 3D VLSI., and . DATE, page 1673-1678. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Implementing digital logic with sinusoidal supplies., , and . DATE, page 315-318. IEEE, (2010)A Boolean satisfiability based solution to the routing and wavelength assignment problem in optical telecommunication networks., , and . ICC, page 1802-1806. IEEE, (2005)High-throughput VLSI implementations of iterative decoders and related code construction problems., , , and . GLOBECOM, page 361-365. IEEE, (2004)Interconnected Tile Standing Wave Resonant Oscillator Based Clock Distribution Circuits., , , and . VLSI Design, page 82-87. IEEE Computer Society, (2011)An Automated Approach for Minimum Jitter Buffered H-Tree Construction., , , , and . VLSI Design, page 76-81. IEEE Computer Society, (2011)