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The mont-blanc prototype: an alternative approach for HPC systems.

N. Rajovic, A. Rico, F. Mantovani, D. Ruiz, J. Vilarrubi, C. Gómez, L. Backes, D. Nieto, H. Servat, X. Martorell, J. Labarta, E. Ayguadé, C. Adeniyi-Jones, S. Derradji, H. Gloaguen, P. Lanucara, N. Sanna, J. Méhaut, K. Pouget, B. Videau, E. Boyer, M. Allalen, A. Auweter, D. Brayford, D. Tafani, V. Weinberg, D. Brömmel, R. Halver, J. Meinke, R. Beivide, M. Benito, E. Vallejo, M. Valero, and A. Ramírez. SC, page 444-455. IEEE Computer Society, (2016)

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Decoupled Vector Architectures.R. Espasa, and M. Valero. HPCA, page 281-290. IEEE Computer Society, (1996)Dynamic Tolerance Region Computing for Multimedia.C. Álvarez, J. Corbal, and M. Valero. IEEE Trans. Computers, 61 (5): 650-665 (2012)A latency-conscious SMT branch prediction architecture.A. Falcón, O. Santana, A. Ramírez, and M. Valero. IJHPCN, 2 (1): 11-21 (2004)Access to streams in multiprocessor systems.M. Valero, M. Peiron, and E. Ayguadé. PDP, page 310-316. IEEE, (1993)Static Locality Analysis for Cache Management.F. Sánchez, A. González, and M. Valero. IEEE PACT, page 261-271. IEEE Computer Society, (1997)Automatic generation of loop scheduling for VLIW.C. Barrado, J. Labarta, E. Ayguadé, and M. Valero. PACT, page 306-309. IFIP Working Group on Algol / ACM, (1995)Virtual registers.A. González, M. Valero, J. González, and T. Arnal. HiPC, page 364-369. IEEE Computer Society, (1997)Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications.S. Isaza, F. Sánchez, G. Gaydadjiev, A. Ramírez, and M. Valero. SAMOS, volume 5114 of Lecture Notes in Computer Science, page 53-64. Springer, (2008)Errata on "Measuring Experimental Error in Microprocessor Simulation".R. Desikan, D. Burger, S. Keckler, J. Cruz, F. Latorre, A. González, and M. Valero. SIGARCH Computer Architecture News, 30 (1): 2-4 (2002)RMS-TM: a comprehensive benchmark suite for transactional memory systems (abstracts only).G. Kestor, V. Karakostas, O. Unsal, A. Cristal, I. Hur, and M. Valero. SIGMETRICS Performance Evaluation Review, 39 (3): 19 (2011)

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The mont-blanc prototype: an alternative approach for HPC systems.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML The mont-blanc prototype: an alternative approach for HPC systems.

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The mont-blanc prototype: an alternative approach for HPC systems.