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Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy.

, , and . ARVLSI, page 59-74. IEEE Computer Society, (2001)

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Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor., , , , and . MICRO, page 96-106. IEEE Computer Society, (2012)Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures., , , , , and . MICRO, page 101-113. IEEE, (2014)Implementing the scale vector-thread processor., , and . ACM Trans. Design Autom. Electr. Syst., 13 (3): 41:1-41:24 (2008)The Vector-Thread Architecture., , , , , , and . ISCA, page 52-63. IEEE Computer Society, (2004)Minimizing energy for wireless web access with bounded slowdown., and . MobiCom, page 119-130. ACM, (2002)Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy., , and . IEEE Trans. VLSI Syst., 15 (9): 1060-1064 (2007)Minimizing Energy for Wireless Web Access with Bounded Slowdown., and . Wireless Networks, 11 (1-2): 135-148 (2005)Cache Refill/Access Decoupling for Vector Machines., , , and . MICRO, page 331-342. IEEE Computer Society, (2004)Convergence and scalarization for data-parallel architectures., , , , and . CGO, page 32:1-32:11. IEEE Computer Society, (2013)Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy., , and . ARVLSI, page 59-74. IEEE Computer Society, (2001)