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Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics., , , , , , , , , and 4 other author(s). IEEE Micro, 29 (4): 8-21 (2009)PyMTL: A Unified Framework for Vertically Integrated Computer Architecture Research., , and . MICRO, page 280-292. IEEE, (2014)The Vector-Thread Architecture., , , , , , and . ISCA, page 52-63. IEEE Computer Society, (2004)Pydgin: generating fast instruction set simulators from simple architecture descriptions with meta-tracing JIT compilers., , and . ISPASS, page 256-267. IEEE Computer Society, (2015)Asymmetry-Aware Work-Stealing Runtimes., , and . ISCA, page 40-52. IEEE Computer Society, (2016)Cache Refill/Access Decoupling for Vector Machines., , , and . MICRO, page 331-342. IEEE Computer Society, (2004)Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators., , , , , , and . ACM Trans. Comput. Syst., 31 (3): 6:1-6:38 (2013)An Architectural Framework for Accelerating Dynamic Parallel Algorithms on Reconfigurable Hardware., , , and . MICRO, page 55-67. IEEE Computer Society, (2018)Designing Chip-Level Nanophotonic Interconnection Networks., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 2 (2): 137-153 (2012)Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics., , , , , , , , , and 4 other author(s). Hot Interconnects, page 21-30. IEEE Computer Society, (2008)