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Disambiguation of "Cazorla, Francisco J."

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A Dual-Criticality Memory Controller (DCmc): Proposal and Evaluation of a Space Case Study.

, , , , , and . RTSS, page 207-217. IEEE Computer Society, (2014)

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J. K\"astner

J. Schwarz

J. K\"astner

J Walter

J. Vogel

 

Other publications of authors with the same name

MLP-Aware Dynamic Cache Partitioning., , , and . PACT, page 418. IEEE Computer Society, (2007)Locality-aware cache random replacement policies., , , and . Journal of Systems Architecture - Embedded Systems Design, (2019)Multicore Early Design Stage Guaranteed Performance Estimates for the Space Domain., , , and . DATE, page 1206-1207. IEEE, (2019)Design and integration of hierarchical-placement multi-level caches for real-time systems., , , and . DATE, page 455-460. IEEE, (2018)Soft Real-Time Scheduling on SMT Processors with Explicit Resource Allocation., , , and . ARCS, volume 4934 of Lecture Notes in Computer Science, page 173-187. Springer, (2008)Speeding up Static Probabilistic Timing Analysis., , , , , and . ARCS, volume 9017 of Lecture Notes in Computer Science, page 236-247. Springer, (2015)Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors., , , , , , and . ISORC, page 208-217. IEEE Computer Society, (2015)Multicore Resource Management., , , , , and . IEEE Micro, 28 (3): 6-16 (2008)QoS for High-Performance SMT Processors in Embedded Systems., , , , , and . IEEE Micro, 24 (4): 24-31 (2004)Resilient random modulo cache memories for probabilistically-analyzable real-time systems., , , and . IOLTS, page 27-32. IEEE, (2016)