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Silicon CMOS devices beyond scaling.

W. Haensch, E. Nowak, R. Dennard, P. Solomon, A. Bryant, O. Dokumaci, A. Kumar, X. Wang, J. Johnson, and M. Fischetti. IBM Journal of Research and Development, 50 (4-5): 339-362 (2006)

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Univ. -Prof. Dr. -Ing. Wolfgang Nowak University of Stuttgart

Comparison of Four Competing Invasion Percolation Models for Gas Flow in Porous MediaI. Banerjee, A. Guthke, C. Van de Ven, K. Mumford, and W. Nowak. Preprint, (2023)

J. K\"astner

J. Schwarz

J. K\"astner

J Walter

Other publications of authors with the same name

CMOS scaling into the 21st century: 0.1 µm and beyond.Y. Taur, Y. Mii, D. Frank, H. Wong, D. Buchanan, S. Wind, S. Rishton, W. Sai-Halasz, and E. Nowak. IBM Journal of Research and Development, 39 (1-2): 245-260 (1995)Overview of gate linewidth control in the manufacture of CMOS logic chips.D. Chesebro, J. Adkisson, L. Clark, S. Eslinger, M. Faucher, S. Holmes, R. Mallette, E. Nowak, E. Sengle, S. Voldman and 1 other author(s). IBM Journal of Research and Development, 39 (1-2): 189-200 (1995)Maintaining the benefits of CMOS scaling when scaling bogs down.E. Nowak. IBM Journal of Research and Development, 46 (2-3): 169-186 (2002)Silicon CMOS devices beyond scaling.W. Haensch, E. Nowak, R. Dennard, P. Solomon, A. Bryant, O. Dokumaci, A. Kumar, X. Wang, J. Johnson, and M. Fischetti. IBM Journal of Research and Development, 50 (4-5): 339-362 (2006)Reduced-voltage power/performance optimization of the 3.6-volt PowerPC 601 Microprocessor.K. Bernstein, J. Bertsch, L. Heller, E. Nowak, and F. White. IBM Journal of Research and Development, 39 (1-2): 33-42 (1995)High-performance CMOS variability in the 65-nm regime and beyond.K. Bernstein, D. Frank, A. Gattiker, W. Haensch, B. Ji, S. Nassif, E. Nowak, D. Pearson, and N. Rohrer. IBM Journal of Research and Development, 50 (4-5): 433-450 (2006)Compact modeling and simulation of PD-SOI MOSFETs: Current status and challenges.J. Goo, R. Williams, G. Workman, Q. Chen, S. Lee, and E. Nowak. CICC, page 265-272. IEEE, (2008)High Performance Double-Gate Device Technology Challenges and Opportunities (invited).M. Leong, H. Wong, E. Nowak, J. Kedzierski, and E. Jones. ISQED, page 492-495. IEEE Computer Society, (2002)RF potential of a 0.18-/spl mu/m CMOS logic device technologyJ. Burghartz, M. Hargrove, C. Webster, R. Groves, M. Keene, K. Jenkins, R. Logan, and E. Nowak. IEEE Transactions on Electron Devices, 47 (4): 864-870 (April 2000)A Retrospective View on the Technology Evolution to Support Low Power Mobile Application.B. Paul, A. Jacob, W. Taylor, R. Mann, J. Versaggi, E. Nowak, and L. Liebmann. J. Low Power Electronics, 14 (3): 374-392 (2018)

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Disambiguation of "Nowak, Edward J."

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Silicon CMOS devices beyond scaling.

Please choose a person to relate this publication to

Univ. -Prof. Dr. -Ing. Wolfgang Nowak University of Stuttgart

J. K\"astner

J. Schwarz

J. K\"astner

J Walter

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Nowak, Edward J."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Silicon CMOS devices beyond scaling.

Please choose a person to relate this publication to

Univ. -Prof. Dr. -Ing. Wolfgang Nowak University of Stuttgart

J. K\"astner

J. Schwarz

J. K\"astner

J Walter

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
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Silicon CMOS devices beyond scaling.