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Voltage Noise in Production Processors., , , , , , and . IEEE Micro, 31 (1): 20-28 (2011)Guest Editors' Introduction: Top Picks from the Computer Architecture Conferences of 2007., , and . IEEE Micro, 28 (1): 8-11 (2008)New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors., , , , , and . IBM Journal of Research and Development, 47 (5-6): 653-670 (2003)Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance., and . HPCA, page 13-22. IEEE Computer Society, (1999)Achieving uniform performance and maximizing throughput in the presence of heterogeneity., , , and . HPCA, page 3-14. IEEE Computer Society, (2011)Multi-accelerator system development with the ShrinkFit acceleration framework., , and . ICCD, page 75-82. IEEE Computer Society, (2014)An event-guided approach to reducing voltage noise in processors., , , , and . DATE, page 160-165. IEEE, (2009)System design considerations for sensor network applications., , and . ISCAS, page 2566-2569. IEEE, (2008)Research Infrastructures for Hardware Accelerators, and . Synthesis Lectures on Computer Architecture Morgan & Claypool Publishers, (2015)Value-based clock gating and operation packing: dynamic strategies for improving processor power and performance., and . ACM Trans. Comput. Syst., 18 (2): 89-126 (2000)