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A SPICE-compatible model of graphene nano-ribbon field-effect transistors enabling circuit-level delay and power analysis under process variation., , , , , and . DATE, page 1789-1794. EDA Consortium San Jose, CA, USA / ACM DL, (2013)FPGA accelerated DNA error correction., , , , and . DATE, page 1371-1376. ACM, (2015)Reconfigurable circuit design with nanomaterials., , and . DATE, page 442-447. IEEE, (2009)A Routing Approach to Reduce Glitches in Low Power FPGAs., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 29 (2): 235-240 (2010)Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages., , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 29 (11): 1709-1722 (2010)Analytical SPICE-Compatible Model of Schottky-Barrier-Type GNRFETs With Performance Analysis., , , , and . IEEE Trans. VLSI Syst., 24 (2): 650-663 (2016)Behavioral-level IP integration in high-level synthesis., , , and . FPT, page 172-175. IEEE, (2015)Design and Evaluation of a Carbon Nanotube-Based Programmable Architecture., , and . International Journal of Parallel Programming, 37 (4): 389-416 (2009)ASAP: Accelerated Short-Read Alignment on Programmable Hardware., , , , , , and . IEEE Trans. Computers, 68 (3): 331-346 (2019)ASAP: Accelerated Short-Read Alignment on Programmable Hardware., , , , , , and . CoRR, (2018)