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Disambiguation of "Gurumani, Swathi T."

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Behavioral-level IP integration in high-level synthesis.

, , , and . FPT, page 172-175. IEEE, (2015)

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T. Ertl

T. Vietor

T. Maier

T. Maier

T. Maier

 

Other publications of authors with the same name

FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow., , , , , , and . IEEE Trans. VLSI Syst., 24 (6): 2220-2233 (2016)Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs., , , , , and . IET Cyper-Phys. Syst.: Theory & Appl., 1 (1): 70-77 (2016)High-level synthesis of multiple dependent CUDA kernels on FPGA., , , , and . ASP-DAC, page 305-312. IEEE, (2013)Fast and effective placement and routing directed high-level synthesis for FPGAs., , , and . FPGA, page 1-10. ACM, (2014)Integrated CUDA-to-FPGA Synthesis with Network-on-Chip., , , , , and . FCCM, page 21-24. IEEE Computer Society, (2014)Designing high-quality hardware on a development effort budget: A study of the current state of high-level synthesis., , , , , , and . ASP-DAC, page 218-225. IEEE, (2016)AutoSLIDE: Automatic Source-Level Instrumentation and Debugging for HLS., , , and . FCCM, page 127-130. IEEE Computer Society, (2016)FCUDA-HB: Hierarchical and Scalable Bus Architecture Generation on FPGAs With the FCUDA Flow., , , , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 35 (12): 2032-2045 (2016)JIT trace-based verification for high-level synthesis., , , , , and . FPT, page 228-231. IEEE, (2015)Real-time system-level implementation of a telepresence robot using an embedded GPU platform., , , , , , , and . DATE, page 1445-1448. IEEE, (2016)