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Analysis of Bridge Defects in STT-MRAM Cells Under Process Variations and a Robust DFT Technique for Their Detection.

V. Champac, A. Gomez, F. Forero, and K. Roy. VLSI-SoC (Selected Papers), volume 561 of IFIP Advances in Information and Communication Technology, page 207-231. Springer, (2018)

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H. Binz

H. Bungartz

Victor Mappes University of Stuttgart

H. Binz

H. Binz

Other publications of authors with the same name

Low voltage testing for interconnect opens under process variations.J. Moreno, V. Champac, and M. Renovell. LATW, page 1-6. IEEE Computer Society, (2012)12th "IEEE Latin-American Test Workshop" Porto de Galinhas, Brazil, 27-30 March 2011.V. Champac, F. de Lima Kastensmidt, L. Poehls, F. Vargas, and Y. Zorian. J. Low Power Electronics, 7 (4): 529-530 (2011)Message from the LATS2015 Chairs.V. Champac, Y. Zorian, L. Pöhls, and V. Agrawal. LATS, page 1. IEEE Computer Society, (2015)Guest Editorial.M. Lubaszewski, and V. Champac. J. Electronic Testing, 17 (2): 83-84 (2001)Guest Editorial.F. Vargas, and V. Champac. J. Electronic Testing, 20 (4): 331-332 (2004)Guest Editorial.V. Champac, and I. Jansch-Pôrto. J. Electronic Testing, 19 (1): 11 (2003)A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines.R. Gómez, A. Girón, and V. Champac. J. Electronic Testing, 24 (6): 529-538 (2008)Testing Skew and Logic Faults in SoC Interconnects.N. Hernandez, and V. Champac. ISVLSI, page 151-156. IEEE Computer Society, (2008)Robust Detection of Bridge Defects in STT-MRAM Cells Under Process Variations.A. Gomez, F. Forero, K. Roy, and V. Champac. VLSI-SoC, page 65-70. IEEE, (2018)Impact of Fin-Height on SRAM Soft Error Sensitivity and Cell Stability.H. Villacorta, J. Segura, and V. Champac. J. Electronic Testing, 32 (3): 307-314 (2016)