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Analysis of the Effect of LUT Size on FPGA Area and Delay Using Theoretical Derivations.

H. Gao, Y. Yang, X. Ma, and G. Dong. ISQED, page 370-374. IEEE Computer Society, (2005)

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Xiliu Yang University of Stuttgart

Yang Wang University of Stuttgart

Guangpu Yang University of Stuttgart

Hsiu-Yu Yang University of Stuttgart

Peihan Yang University of Stuttgart

Other publications of authors with the same name

Design of a low power GPS receiver in 0.18 µm CMOS technology with a SigmaDeltafractional-N synthesizer.D. Li, Y. Yang, J. an Wang, B. Li, Q. Long, J. Wei, N. di Wang, L. Wang, Q. kun Liu, and D. long Zhang. Journal of Zhejiang University - Science C, 11 (6): 444-449 (2010)Cluster mesh: a topology for three-dimensional network-on-chip.J. Wang, H. Gu, and Y. Yang. IEICE Electronic Express, 9 (15): 1254-1259 (2012)A bufferless optical network-on-chip router.N. Zhang, H. Gu, Y. Yang, Z. Chen, and K. Chen. IEICE Electronic Express, 10 (21): 20130681 (2013)A multi-wavelength communication strategy for 2D-mesh Network-on-Chip.X. Yu, H. Gu, Y. Yang, L. Bai, and H. You. IEICE Electronic Express, 9 (7): 706-711 (2012)A low-jitter pulsewidth control loop with high supply noise rejection.S. Liu, Z. Zhu, H. Gu, and Y. Yang. IEICE Electronic Express, 10 (18): 20130619 (2013)A Low Offset High Speed Comparator for Pipeline ADC.Z. Zhu, H. Wu, G. Yu, Y. Li, L. Liu, and Y. Yang. Journal of Circuits, Systems, and Computers, (2013)A 2.1-Channel Class-D Amplifier Exploited Coupling Virtual-Audio-Image to Enhance Stereo.L. Liu, S. Deng, Z. Zhu, and Y. Yang. IEEE Trans. on Circuits and Systems, 61-II (5): 324-328 (2014)ESLRAS: A Lightweight RFID Authentication Scheme with High Efficiency and Strong Security for Internet of Things.K. Fan, J. Li, H. Li, X. Liang, X. Shen, and Y. Yang. INCoS, page 323-328. IEEE, (2012)A Novel R-C Combination Based Pseudo-differential SAR A/D Converter in 90nm CMOS Process.X. Tong, Y. Yang, Z. Zhu, Y. Xiao, and J. Chen. PACCS, page 289-292. IEEE Computer Society, (2009)An area-efficient and high speed multiplexer for battery monitor system.Q. Zhang, Y. Yang, and C. Chai. IEICE Electronic Express, 13 (8): 20160120 (2016)

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Disambiguation of "Yang, Yintang"

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Analysis of the Effect of LUT Size on FPGA Area and Delay Using Theoretical Derivations.

Please choose a person to relate this publication to

Xiliu Yang University of Stuttgart

Yang Wang University of Stuttgart

Guangpu Yang University of Stuttgart

Hsiu-Yu Yang University of Stuttgart

Peihan Yang University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Yang, Yintang"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Analysis of the Effect of LUT Size on FPGA Area and Delay Using Theoretical Derivations.

Please choose a person to relate this publication to

Xiliu Yang University of Stuttgart

Yang Wang University of Stuttgart

Guangpu Yang University of Stuttgart

Hsiu-Yu Yang University of Stuttgart

Peihan Yang University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Analysis of the Effect of LUT Size on FPGA Area and Delay Using Theoretical Derivations.