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Optimizations Enabled by a Decoupled Front-End Architecture., , and . IEEE Trans. Computers, 50 (4): 338-355 (2001)Challenges in processor modeling and validation Guest Editors?? introduction., , and . IEEE Micro, 19 (3): 9-14 (1999)DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design.. MICRO, page 196-207. ACM/IEEE Computer Society, (1999)Efficient Dynamic Scheduling Through Tag Elimination., and . ISCA, page 37-46. IEEE Computer Society, (2002)Microprocessor Verification via Feedback-Adjusted Markov Models., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 26 (6): 1126-1138 (2007)Reliable Systems on Unreliable Fabrics., , , and . IEEE Design & Test of Computers, 25 (4): 322-332 (2008)Exploring Variability and Performance in a Sub-200-mV Processor., , , , , , , , , and 2 other author(s). J. Solid-State Circuits, 43 (4): 881-891 (2008)Leakage Current: Moore's Law Meets Static Power., , , , , , , , and . IEEE Computer, 36 (12): 68-75 (2003)DVS for On-Chip Bus Designs Based on Timing Error Correction, , , , and . CoRR, (2007)Ozone: Efficient Execution with Zero Timing Leakage for Modern Microarchitectures., and . CoRR, (2017)