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Disambiguation of "Kastner, Ryan"

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Bit Error Rate, Power and Area Analysis of Multiple FPGA Implementations of Underwater FSK.

, , , and . ERSA, page 136-142. CSREA Press, (2009)

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J. K\"astner

Univ. -Prof. Dr. Johannes Kästner University of Stuttgart

J. K\"astner

J. K\"astner

Johannes K\"astner

 

Other publications of authors with the same name

FPGA Accelerated Online Boosting for Multi-target Tracking., , , and . FCCM, page 165-168. IEEE Computer Society, (2014)Layout driven data communication optimization for high level synthesis., , , , , , and . DATE, page 1185-1190. European Design and Automation Association, Leuven, Belgium, (2006)Instruction Generation for Hybrid Reconfigurable Systems., , , and . ICCAD, page 127-. IEEE Computer Society, (2001)Storage assignment during high-level synthesis for configurable architectures., , and . ICCAD, page 3-6. IEEE Computer Society, (2005)Hardware Implementation of Symbol Synchronization for Underwater FSK., , , and . SUTC/UMC, page 82-88. IEEE Computer Society, (2010)Real-time 3D reconstruction for FPGAs: A case study for evaluating the performance, area, and programmability trade-offs of the Altera OpenCL SDK., , , , , and . FPT, page 326-329. IEEE, (2014)Eliminating Timing Information Flows in a Mix-Trusted System-on-Chip., , and . IEEE Design & Test, 30 (2): 55-62 (2013)Identifying and Measuring Security Critical Path for Uncovering Circuit Vulnerabilities., , and . MTV, page 62-67. IEEE Computer Society, (2017)Resolve: Generation of High-Performance Sorting Architectures from High-Level Synthesis., , , , , , and . FPGA, page 195-204. ACM, (2016)A FPGA Accelerator for Real-Time 3D Non-rigid Registration Using Tree Reweighted Message Passing and Dynamic Markov Random Field Generation., , and . FPL, page 335-342. IEEE Computer Society, (2018)